This invention relates to a timing circuit for synchronizing a digital data processor and input data at the single line serial interface of the digital data processor.
There have been timing circuits for single line serial data used at input interfaces of digital data processors. FIG. 1 illustrates one of such circuits by way of example.
Referring to FIG. 1, a data sampling circuit A is composed of a delay flip-flop FF1a of a positive logic for sampling input data input from an input data terminal 1 with reference clock pulses input from a reference clock input terminal 2.
A data edge detection circuit B is composed of a delay flip-flop FF2a of a negative logic and an exclusive negative OR gate EX-NORa to generate data edge detection signals synchronously with the reference clock pulses.
A synchronous pulse generation circuit C is composed of an up counter COUNTa and it receives the data edge detection signals from the data edge detection circuit B as reset input and generates repetitive pulses of equal period. In many cases, the period of the repetitive pulses is set so as to be coincident with a width of the minimum unit pulse.
A waveform shaping circuit D is composed of a delay flip-flop FF4a of a positive logic for eliminating hazardous or extraneous signals, so-called "glitch noise".
An output timing circuit E is composed of a delay flip-flop circuit FF3a of a positive logic for adjusting timing of output data and synchronous output clock pulses from the waveform shaping circuit D.
In this case, FF2a is the delay flip-flop circuit operated by the negative logic and FF1a, FF3a and FF4a are the delay flip-flop circuits operated by the positive logic. EX-NORa is the exclusive negative OR gate. COUNTa is the counter whose output changes at count "2".
With the timing circuit of the prior art shown in FIG. 1, the input data fed from the input data terminal 1 is sampled in the data sampling circuit A and then transmitted through the data edge detection circuit B and the output timing circuit E and further through the output data terminal 3 to a digital data processor.
Moreover, the reference clock pulses input from the reference clock input terminal 2 are criteria for operations of this timing circuit and supplied to the means FF1a, FF2a, COUNTa, FF3a and FF4a. In the flip-flop FF1a, the supplied clock pulses are used as sampling clock pulses.
The repetition pulses produced in the synchronizing pulse generation circuit C are transmitted through the wave shaping circuit D and further through the synchronous clock output terminal 4 to the digital data processor.
In the timing circuit of the prior art shown in FIG. 1, assuming that L is the minimum unit pulse width of the input data from the input data terminal 1, the input data is constituted by pulses having a width of nL (n is a natural number). Moreover, when the reference clock pulse is synchronized at the pulse width of L/4, if the input waveform input from the input data terminal 1 is distorted more than .+-.1/4 L due to parasitic electrostatic capacity of signal lines and the like, the normal or proper output cannot be obtained from the synchronous clock output terminal 4. Therefore, there is a problem in this circuit of the prior art in that an allowable tolerance for distortion of pulse widths of the input data is insufficient.
FIG. 2 illustrates a timing chart showing the normal operation of the circuit shown in FIG. 1, while FIG. 3 illustrates, by way of example, the problem of the circuit shown in FIG. 1.
In FIG. 2, the unit data length is L(s), and the period of the reference clock pulse is L/4(s). The period of the synchronous clock pulse is L(s) and one clock pulse corresponds to one datum.
In FIG. 3, the length of the first datum is 5/8 L(s) which is 3/8 L(s) shorter than the pulse width L(s) of the first datum without distortion. On the other hand, the length of the fifth datum is 11/8 L(s) which is 3/8 L(s) longer than that of the fifth datum without distortion. The lengths of the second and third data are 19/8 L(s) which are 3/8 L(s) longer than the pulse width 2 L(s) of the second and third data without distortion. On the other hand, the lengths of the sixth and seventh data are 13/8 L(s) which are 3/8 L(s) shorter than those of the sixth and seventh data without distortion. The period of the reference clock pulse is 1/4 L(s) which is equal to that in FIG. 2.
Signals at (a), (b), (c) and (d) are produced by the rising of output signals caused by counting operation of the counter COUNTa and trailing of output signals caused at the same time by reset signals input by the gate EX-NORa. Therefore, these signals are unstable because they occur only when the rising and trailing of said two output signals is coincident with each other in timing. Such hazardous or extraneous signals must be eliminated because they may cause malfunction of the circuit in the next stage. For example, the signal (b) is eliminated, because data sampling is effected in the flip-flop FF3a of the next stage during the time from T to T'. The same is applied to the signals (a), (c) and (d).
As a result of elimination of the signals (a) and (d), the signals to be inherently output at the positions (e) and (f) could not be obtained so that synchronous clock pulses corresponding to the first and seventh data do not occur. Accordingly, the object of this timing adjusting circuit of the prior art could not be accomplished.